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XMEGA A [MANUAL]
8077I–AVR–11/2012
15.7.5 DTBOTH – Dead-time Concurrent Write to Both Sides register
Bit 7:0 – DTBOTH: Dead-time Both Sides
Writing to this register will update the DTHS and DTLS registers at the same time (i.e., at the same I/O write access).
15.7.6 DTBOTHBUF – Dead-time Concurrent Write to Both Sides Buffer register
Bit 7:0 – DTBOTHBUF: Dead-time Both Sides Buffer
Writing to this memory location will update the DTHSBUF and DTLSBUF registers at the same time (i.e., at the same I/O
write access).
15.7.7 DTLS – Dead-time Low Side register
Bit 7:0 – DTLS: Dead-time Low Side
This register holds the number of peripheral clock cycles for the dead-time low side.
15.7.8 DTHS – Dead-time High Side register
Bit 7:0 – DTHS: Dead-time High Side
This register holds the number of peripheral clock cycles for the dead-time high side.
Bit
7
65
43
21
0
+0x06
DTBOTH[7:0]
Read/Write
R/W
Initial Value
0
Bit
7654321
0
+0x07
DTBOTHBUF[7:0]
Read/Write
R/W
Initial Value
0000000
0
Bit
7
6
543210
+0x08
DTLS[7:0]
Read/Write
R/W
Initial Value
0
000000
Bit
765
43210
+0x09
DTHS[7:0]
Read/Write
R/W
Initial Value
000
00000